FPGAs can become more programmable by adding a soft-core RISC-V processor. Bluespec’s Loren Hobbs discusses how to make it ...

Regular readers, with some familiarity with Tenstorrent’s recent projects, won’t be surprised that next-gen semiconductors ...

Arteris and MIPS today announced a partnership to provide a pre-verified reference platform to support mutual customers. The ...

Finding out if a processor implementation matches the specification is important, but conformance testing is currently not ...

Andes Technology's Yueh-Feng Lee presented LLM Inference on RISC-V Embedded CPUs. This presentation highlights the ...

Andes Technology unveiled its AndesCore 32-bit, 8-stage D45-SE RISC-V processor with ISO 26262 ASIL-D certification.

MIPS, a developer of IP compute cores, announced today the general availability(GA) launch of the MIPS P8700 Series RISC-V ...

Designed to meet the low-latency, highly intensive data movement demands of the most advanced automotive applications such as ...

Japan's Leading-edge Semiconductor Technology Center (LSTC) has forged a strategic partnership with Canadian chip designer ...

MicroPython v1.24 firmware adds support for Raspberry Pi RP2350 and Espressif ESP32-C6 microcontrollers, RISC-V improvements, and more.

Signaloid C0-microSD is a tiny iCE40UP5K FPGA system-on-module (SoM) in a microSD card form factor preloaded with a RISC-V ...